Job Descriptions:
 Logic Verification Engineer
Title: Verification Engineer/Sr. Verification Engineer
Location: Mountain View, CA office
Department: Hardware Engineering (Network & Communications Div)
Job Code: JobPostDV1001
Description:
Contributes as a verification engineer as part of the world class leading edge Embedded processor design team working on the 3rd generation of the Octeon product family. This includes developing the architecture for a functional verification environment including reference models, bus functional monitors and drivers. Writing a verification test plan using random techniques and coverage analysis and working with designers to ensure it is complete. Build a constrained random environment for various functional blocks as well as for full chip testing. Developing tests and tuning the environment to achieve the coverage goals. Debugging failures and working with the logic designers to resolve the issues.
Requirements:
- BSCS/EE or equivalent required with 3 - 7+ years of logic verification experience of functional units in Microprocessor based SOC products.
- Strong programming skills using C++ and Verilog.
- Experience with writing a detailed test plan and building a sophisticated directed random verification environment.
- Must possess good communication skills, self driven individual and a good team player
- Working knowledge in one or more of the following: Processor architecture, SOC components, SOC inter-connect busses and memory interfaces.
- Experience with System Verilog is a plus.
- Experience in working with EDA verification tools is a plus.(e,g; waveform viewers, coverage tools etc;)
- Coding in scripting languages like Perl, Tcl & UNIX Shell etc;.
- Good understanding of Linux O.S. and networking protocols is a plus.
Please add reference job code JobPostDV1001on subject line of email.
Sr. Manager/Dir System Software
Title: Sr. Manager/Dir System Software
Location: Mountain View, CA office
Department: Software
Description:
Lead position to architect and manage development, testing and integration of embedded software for a H.264 based CODECs SoC and reference designs. Candidate will also be expected to have strong technical background to provide oversight and guidance in system and software architectural definition.
Responsibilities:
- Manage a software team with engineers in the local office and offshore.
- Coordinate development responsibilities and schedules across the team. Interface with Hardware, Marketing, and Sales teams to plan software development agenda.
- Review, provide guidance and/or assist technically with software specification and architectural development; coding design guidelines
- Coordinate test and integration plan with hardware team.
- Provide second-line-of-defense (after Application Engineering) engineering support for SW problems encountered by customers
- Specifically:
- Develop platform independent drivers to run under Linux and Windows OS’s running on ARM and x86 CPUs.
- Integrate the networking stack
- Develop application specific components: i.e. traffic shaping, QoS, and packet forwarding.
- Develop GUI
Requirements:
- BS or MS in computer science or electrical engineering
- 10+ years of experience in software development, testing and integration
- 5+ years experience in managing a small multi-site team
- Experience in C/C++ and scripting (i.e. Perl)
- Experience in developing Linux and Windows drivers
- Experience in GUI development
- In depth knowledge of networking protocols: RTP, TCP/UDP, IP, HTTPS
- Experience with wired and/or wireless networking
- Good understanding of PCI/PCIe, USB
- Familiarity with audio and video codecs
- Familiarity with VoIP, Security (VPN, firewall, etc) is a plus
- The candidate must be a self-starter with good communication skills
Sr. Test Engineer
Title: Sr. Test Engineer
Location: Mountain View, CA office
Department: Software
Responsibilities:
As a Senior Test Engineer you will be responsible
for test program development on the Agilent 93K test platform.
Other responsibilities include
- Design tester hardware for high speed testing.
- Develop characterization, production, and wafer sort
test programs.
- Create all the documentation for detail test plans and
test methodologies to meet product specifications.
- Involved in the testability review (DFT & DFM) of
complex processor devices.
- Test pattern conversion from design simulation environment
to ATE format.
- Test time reduction, yield improvement, and release of
production test programs with product engineers.
Requirements:
- BS or MS (Preferred)
- Minimum 6+ yrs of test program development experience
on the Agilent 93K ATE test platform. Strong knowledge of
C/C++, Perl, and Unix environment.
Sr. RTL Design Engineer
Title: Sr. RTL Design Engineer
Location: Mountain View, CA office
Department: Hardware Engineering (Network & Communications
Div)
Requirements:
- BS/MS in EE or equivalent required with 10+years of experience in RTL design of submicron SOC products (e,g; Microprocessor based SOC’s).
- Experience in Micro-architecture for the complex Custom/ASIC products focusing in any one/more areas: NPU, Embedded Processors, DSP, Graphics and/or general purpose microprocessors.
- Strong hands on RTL design experience, Synthesis, static timing closure, formal verification, gate level simulations & block level function verification.
- Design knowledge of one/more industry standard bus interfaces ( PCIe , SPI, SRIO, USB, XAUI etc; ) and memory interfaces (DDR2, DDR3 etc;).
- Experience in interfacing with architecture and Physical implementation teams.
- Hands on experience for all aspects of chip development process with proficiency in front end design tools and methodologies.
- Experience in designing high speed (>1 GHz) /high performance embedded processor SOC products is a plus.
- Experience with IP selection and interaction with 3 rd party IP vendors with respect to front end design, timing views and associated integration is a plus.
- Coding in scripting languages such as Perl, Tcl and UNIX shell etc;
- Have interacted with silicon operations team to support silicon bring-up and characterization of the product.
- Must possess good communication skills.
- Self driven individual and a good team player.
Description:
As a senior RTL designer, contribute & lead the development of one or more Coprocessor units, industry standard high speed serial bus interfaces for Cavium’s next generation Multi-core embedded MIPS64 processor family targeted at Networking, Storage, Security & Wireless applications in the state of the art deep sub-micron CMOS process technologies. Work with the architecture team and as a design team member, shape the micro-architecture of the chip, and write specifications for the relevant block, micro-architecture of the block, design implementation using RTL coding techniques, Synthesis, place & route and timing sign off.
Individual also works with the verification team on some pre-silicon verification tasks such as reviewing the verification test plan, coverage analysis and full chip simulation plus debug. Also, work with the physical design teams in aiding the implementation of the functional blocks.
Please add reference job code
CARTL02 on subject line of email.
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